The present invention relates to semiconductor device manufacturing, and more specifically, to metal silicate spacers for fully aligned vias in interconnect structures.
Semiconductor integrated circuits or chips include a number of devices that are connected by a wiring interconnect network. When the devices are arranged on multiple levels, a given interconnect can traverse the chip across a given level or between levels through vias. Proper alignment of the vias with the interconnect below is required, because overlay error can affect reliability. Overlay error refers to the situation in which the via is not aligned with the interconnect below but can also refer to misalignment of the via such that some of the interconnect formed in the via is adjacent to rather than entirely above the interconnect on the lower level. When the intersection between the via and the interconnect in the level below is too small, electromigration failure can result. When the via is misaligned and the misalignment affects the spacing between adjacent interconnects, then time dependent dielectric breakdown can result. Thus, proper alignment of vias with their associated lower-level interconnects is of interest.